Fujitsu F2MC-16LX Hardware Manual page 640

16-bit microcontroller mb90330 series
Hide thumbs Also See for F2MC-16LX:
Table of Contents

Advertisement

APPENDIX
Register indirect with displacement (@RWi+disp8 i=0 to 7, @RWj+disp16 j=0 to 3)
Memory is accessed using the address obtained by adding an offset to the contents of general-purpose
register RWj. There are two types of displacement, byte and word. Bytes and words are added as signed
numbers.Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4 or
RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is
used, or additional data bank register (ADB) when RW2 or RW6 is used.
Figure B.4-3 Example of Register Indirect with Displacement (@RWi + disp8i = 0 to 7, @RWj + disp16j = 0
MOVW A, @RW1+10H
Register indirect (long) with displacement (@RLi + disp8i = 0 to 3)
Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the
contents of general-purpose register RLi. Displacement is added as an 8-bit signed number.
Figure B.4-4 Example of Register Indirect (Long) with Displacement (@RLi + disp8i = 0 - 3)
MOVW A, @RL2+25H
Program counter indirect with displacement (@PC + disp16)
Memory is accessed using the address indicated by (instruction address + 4 + disp16). The displacement is
one word long. Bit 23 to Bit 16 of the address are specified by the program bank register (PCB). Note that
the operand address of each of the following instructions is not deemed to be (next instruction address +
disp16):
• DBNZ eam,rel
• CBNE eam,#imm8,rel
• MOV
624
(This instruction reads data by register indirect addressing
with an offset and stores it in A.)
Before execution
A
RW1
D 3 0 F
After execution
A
RW1
D 3 0 F
(This instruction reads data by long register indirect addressing
with an offset and stores it in A.)
A
0 7 1 6
Before execution
RL2
F 3 8 2
After execution
A
2 5 3 4
RL2
F 3 8 2
DWBNZ eam,rel
CWBNE eam,#imm16,rel
eam,#imm8
MOVW eam,#imm16
to 3)
0 7 1 6
2 5 3 4
DTB
7 8
78D320
78D31F
(+10
)
H
2 5 3 4
F F E E
DTB
7 8
2 5 3 4
Memory space
824B28
F F
4 B 0 2
H
824B27
E E
H
(+25
)
H
F F E E
4 B 0 2
Memory space
F F
H
E E
H

Advertisement

Table of Contents
loading

Table of Contents