Writing Data To Flash Memory - Fujitsu F2MC-16LX Hardware Manual

25.6.2

Writing Data to Flash Memory

The procedure to issue the write command and write data into the flash memory is
described.
Writing Data to Flash Memory
To start the data write automatic algorithm, you may send the write command sequentially in the command
sequence table (See Table 25.4-1) to the target sector in the flash memory. When data writing to the target
address ends at the forth cycle, the automatic algorithm is activated and then the automatic writing starts.
How to specify address
Only an even address is acceptable for the write address specified in the data write cycle. An odd address
does not allow you to write properly. In other words, writing into an even address per word data is required.
However, execution of one programming command, permits programming of only one word for data.
Notes on data programming
Data "0" cannot be returned to data "1" by writing. If you write data "1" into data "0", the data polling
algorithm (DQ7) or the toggle operation (DQ5) do not finish and the flash memory device is determined to
have a defect, and as a result writing exceeds the predefined time, and the timing limit excess. However,
when data is read while read/reset, data is "0". You can change data from "0" to "1" only in the erase
operation.
All commands are disregarded while the automatic write command is being executed. Please note that if the
hardware reset is started while writing, the address data currently being written is not secured.
Writing Procedure of Flash Memory
Figure 25.6-1 shows an Procedure example for writing to flash memory. You may determine the state of
the automatic algorithm in the flash memory by using the hardware sequence flag (See "25.5 Check the
Execution State of Automatic Algorithm"). In this section data polling flag (DQ7) is used to confirm an end
of writing.
Flag check data should be read from the address where data was last written.
As the data polling flag (DQ7) is changed along with the timing limit excess flag (DQ5), you need to
recheck the data polling flag bit (DQ7) even if the timing limit excess flag (DQ5) is "1".
Likewise, the toggle bit flag (DQ6) terminates the toggle operation just when the timing limit excess flag
(DQ5) changes into "1", you need to recheck the toggle bit flag (DQ6).
CHAPTER 25 3M-BIT FLASH MEMORY
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