Ppg0 To Ppg5 Output Control Register (Ppg01/Ppg23/Ppg45) - Fujitsu F2MC-16LX Hardware Manual

17.2.3 PPG0 to PPG5 Output Control Register (PPG01/PPG23/
PPG45)
Configuration and functions of PPG0 to PPG5 output control register (PPG01/PPG23/
PPG45) are described.

PPG0 to PPG5 Output Control Register (PPG01/PPG23/PPG45)

Figure 17.2-4 shows the bit configuration of the PPG0 to PPG5 output control registers (PPG01/PPG23/
PPG45).
Figure 17.2-4 PPG0 to PPG5 Output Control Register (PPG01/PPG23/PPG45)
ch0, 1 : 00004C
ch2, 3 : 00004E
ch4, 5 : 000050
PPG0 to PPG5 output control register (PPG01/PPG23/PPG45)
[bit 7 to bit 5] PCS2 to PCS0: ppg Count Select (count clock selection)
Selects the operation clock of the ch1, ch3, and ch5 down counters.
PCS2
0
0
0
0
1
1
• These bits are initialized to "000
• Reading and writing are allowed.
Note:
Since the PPG of ch1, ch3, and ch5 operates by receiving the count clock from the ch0, ch2, and
ch4 in the 8-bit prescaler + 8-bit PPG mode and the 16-bit PPG mode, the specified PCS2 to PCS0
bits become invalid.
7 6 5
H PCS2 PCS1 PCS0 PCM2
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
H
(0) (0) (0)
(0)
PCS1 PCS0
0 0 Peripheral Clock (41.6 ns machine clock 24 MHz time) in surrounding
0 1 Peripheral Clock /2 (83.3 ns machine clock 24 MHz time) in surrounding
1 0 Peripheral Clock /4 (167 ns machine clock 24 MHz time) in surrounding
1 1 Peripheral Clock /8 (333 ns machine clock 24 MHz time) in surrounding
0 0 Peripheral Clock /16 (667 ns machine clock 24 MHz time) in surrounding
Input clock from time base counter
1 1
9
× 167 ns=85µs field oscillation 6 MHz time)
(2
B
1
4 3 2
PCM1 PCM0
Reserved Reserved
(0) (0) (X)
Operating mode
" at reset.
CHAPTER 17 8/16-BIT PPG TIMER
0
PPG01/PPG23/PPG45
PPG Output control register
Read/Write
(X)
Initial value
413