I 2 C Bus Control Register 0 To 2 (Ibcr0 To Ibcr2) - Fujitsu F2MC-16LX Hardware Manual

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22.2.2 I C Bus Control Register 0 to 2 (IBCR0 to IBCR2)
The configuration and functions of I
described.
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I C Bus Control Register 0 to 2 (IBCR0 to IBCR2)
Figure 22.2-3 shows the bit configuration of bus control register 0 to 2(IBCR0 to IBCR2).
Figure 22.2-3 Bit Configuration of I
ch0:000071
ch1:000077
ch2:00007D
The function of each bit of the bus control registers 0 to 2 (IBCR0 to IBCR2) is described as follows:
[bit 15] BER: Bus ERror
It is Bus error Interrupt request flag. Functions in writing phase differ from those as follows.
(at writing)
0
1
(at reading)
0
1
If BER bit is set, EN bit of ICCR register is cleared, the I
transfer is terminated.
[bit 14] BEIE: Bus Error Interrupt Enable
It is bus error Interrupt enable bit.
0
1
The interruption is generated if the BER bit is "1" when this bit is "1".
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C bus control register 0 to 2 (IBCR0 to IBCR2) are
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C Bus Control Register 0 to 2 (IBCR0 to IBCR2)
15 14 13 12
H
BER BEIE SCC MSS ACK GCAA INTE INT
H
R/W R/W R/W R/W R/W R/W R/W R/W
H
Clear bus error interrupt request flag.
No effect on operation
The bus error is not detected.
Illegal start and stop condition was detected during data transfer.
Bus error interrupt disabled
Bus error interrupt enabled
IBCR0 to IBCR2
11 10 9 8
2
I
Initial value
Read/Write
2
C interface goes into a halted state, and data
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CHAPTER 22 I C INTERFACE
C Bus status register
00000000
B
527