External Memory Access - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 7 MODE SETTING
7.4

External Memory Access

The block diagram of the external memory access, the configuration/function of the
register, and the operation of the external memory access are described.
I/O Signal Terminal of External Memory Access
2
F MC-16LX provides the following address/data/control signal to access the external memory/peripheral.
• CLK(P57): Machine cycle clock (KBP) is output.
• RDY(P56): It is an external ready input terminal.
• (HAK)(P55): It is a hold acknowledge output pin.
• HRQ(P54): It is a holding request input terminal.
• (WRH)(P53): It is a writing signal of a data bus upper byte.
• (WRL)(P52): It is a data bus lower 8 bit write signal.
• (RD)(P51): It is a reading signal.
• ALE(P50): It is an address latch permission signal (enabled in the multiplex mode).
Block Diagram
Figure 7.4-1 shows the block diagram of the external bus pin control circuit.
Figure 7.4-1 Block Diagram of External Bus Pin Control Circuit
Internal
address bus
Internal
data bus
Access control
182
P4
P3
P2
P1
P0
P0 data
P0 direction
Data control
Address control
Access control
P5
P5
P0