Watch Mode - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5.3

Watch Mode

The watch mode terminates all the operations other than the sub clock and the watch
timer, where almost all the functions of the chip are terminated.
Transition to Watch Mode
In the sub clock mode (the sub clock display bit of the clock selection register (CKSCR) (SCS)=0), when
you write "0" into the watch/timebase timer mode bit (TMD) of the low-power consumption mode control
register (LPMCR the transition to the watch mode).
Data retention function
In the watch mode, contents of the dedicated registers such as accumulators and the internal RAM are held
unchanged.
Holding function
During the watch mode, the external bus hold function halts, thereby neglecting a hold request if a hold
request is input. If a hold request is input during the transition to the watch mode, the condition of bus high-
impedance is maintained and the HAK signal may not become "L".
Operation during an interrupt request
When "0" is set to the TMD bit of the LPMCR register, transition to the watch mode is not made if there is
an interrupt request.
Pin state setting
You can set whether the external pin in the watch mode should be retained in the preceding state or become
to the high impedance state by controlling the pin state specification bit (SPL) in the LPMCR register.
Cancellation of Watch Mode
The low-power consumption circuit cancels the watch mode by generating a reset input or an interrupt
request.
Return by Reset
When clearing watch mode by a reset cause, transition occurs to oscillation stabilization wait reset state
after clearing watch mode. The reset sequence is executed after the oscillation stabilization wait time.
Return by interrupt
If there is an interrupt request higher than level 7 from peripheral circuits and others in the watch mode
(except for IL2, IL1, IL0 of the interrupt control register (ICR) = "111
control circuit cancels the watch mode and immediately changes to the sub clock mode. After transiting to
sub clock mode, the action is the same as for ordinary interrupt processing. When an interrupt is acceptable
by settings in the I flag of the condition code register (CCR), the interrupt level mask register (ILM), and
the interrupt control register (ICR), interrupt processing is carried out. When an interrupt is not acceptable,
processing from the instruction succeeding the one caused to enter clock mode continues.
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"), the low-power consumption
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