Dma Permission Register (Derh/Derl) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 3 INTERRUPT
3.8.2.4

DMA Permission Register (DERH/DERL)

DMA permission register (DERH/DERL) enables the DMA transfer.
When "1" is set to this register, the interrupt request, which is the DMA transfer
request, generates to the corresponding channel, and starts the DMA transfer.
DMA Permission Register (DERH/DERL)
Figure 3.8-5 Bit Configuration of DMA Permission Register (DERH/DERL)
0000AD
EN15
H
R/W
0000AC
EN7
H
R/W
R/W : Readable/Writable
[bit15 to bit0] ENx: DMA permission
ENx bit
0 [Initial value] This bit does not execute the DMA transfer.
The interrupt request from the resource is handled as a DMA activation request, and the
interrupt request is output to the interrupt controller at the end of DMA transfer.
1
When the number of DMA transfer bytes reaches 0, or a STOP request from the resource
stops DMA transfer, this is cleared to '0'.
Notes:
• To write data to the DER, use a read modify write (RMW) instruction.
• To change the mode to sleep or stop make sure that the ENx bit has been set to "0".
94
15 14 13 12
EN14 EN13 EN12
R/W R/W R/W
7 6 5 4
EN5 EN4
EN6
R/W R/W R/W
11 10 9
EN8
EN11 EN10 EN9
R/W R/W R/W R/W
3 2 1
EN3 EN1
EN2 EN0
R/W R/W R/W R/W
Function
8
DERH
Initial value 00000000
0
DERL
Initial value 00000000
B
B