Fujitsu F2MC-16LX Hardware Manual page 555

Figure 22.3-2 1-byte Transfer Flow from Slave to Master
Master
IDAR: Writing
MSS: Writing 1
BB set,TRX set
LRB reset
INT set,TRX reset
INT: Writing 0
INT set
IDAR: Read
MSS: Writing 0
INT reset
BB reset,TRX reset
Start
Start condition
Address data transfer
Acknowledgement
Interrupt
Data transfer
Negative acknowledgement
Interrupt
Stop condition
End
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CHAPTER 22 I C INTERFACE
Slave
BB set,TRX set
AAS reset
INT set,TRX set
IDAR: Writing
INT: Writing 0
LRB set,TRX set
INT set
INT: Writing 0
BB reset,TRX reset
AAS reset
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