Fujitsu F2MC-16LX Hardware Manual page 262

CHAPTER 12 16-BIT I/O TIMER
[bit 2 to bit 0] CLK2,CLK1,CLK0 (Count clock cycle selection bit)
Select count clock of 16-bit free-run timer. Since the clock is changed immediately after writing into the
CLK2, CLK1, and CLK0 bits you must change it when the output compare and input capture are in
stopping state.
CLK2
0
0
0
0
1
1
1
1
246
Count
CLK1 CLK0
Clock
φ
0 0
φ/2
0 1
φ/4
1 0
φ/8
1 1
φ/16
0 0
φ/32
0 1
φ/64
1 0
φ/128
1 1
φ=24 MHz φ=12 MHz
41.7 ns 83.3 ns
0.17 µs
83.3 ns
0.17 µs 0.33 µs
0.33 µs 0.67 µs
0.67 µs 1.33 µs
1.33 µs 2.67 µs
2.67 µs 5.33 µs
5.33 µs 10.7 µs
φ=6 MHz φ=3 MHz
0.17 µs 0.33 µs
0.33 µs 0.67 µs
0.67 µs 1.33 µs
1.33 µs 2.67 µs
2.67 µs 5.33 µs
5.33 µs 10.7 µs
10.7 µs 21.3 µs
21.3 µs 42.7 µs