Fujitsu F2MC-16LX Hardware Manual page 691

Conversion Operation
Conversion Operation Using µDMAC or EI
Count Clock
Count Clock and Maximum Cycle
................................. 369, 418
Count Clock Selection
Count Timing
Count Timing of Free-run Timer
Counter
Counter Operation Mode
State Transition of Counter Operation
Counter Operation
Measurement Mode and Counter Operation
CPCLR
Compare Clear Register (CPCLR)
CPU
Outline Specification of CPU
CPU Intermittent Operation
CPU Intermittent Operation Mode
CPU Operation Mode
CPU Operation Modes and Current Consumption
Current Consumption
CPU Operation Modes and Current Consumption
Cycle
Calculation Method of Pulse Width/cycle
Range of Count at Pulse Width/cycle
Cycle Count
Calculating the Execution Cycle Count
........................................ 629
Execution Cycle Count
D
Data Bus
External 16-Bit Bus Mode (External Data Bus 16-Bit/
Multiplex Mode)
Pin State in External Bus 16-bit Data Bus and Multiplex
16-bit External Bus Mode
Pin State in External Bus 16-bit Data Bus and Non-multiplex
16-bit External Bus Mode
Pin State in External Bus 8-bit Data Bus and Multiplex 8-bit
External Bus Mode
Pin State in External Bus 8-bit Data Bus and Non-multiplex
8-bit External Bus Mode
Data Counter
.............................................. 78
Data Counter (DCT)
Data Number Automatic Transfer
Data Number Automatic Transfer Mode
Data Packet
....................................................... 342
Data Packet
Data Polling Flag
State Transition of Data Polling Flag (DQ7)
Data Register
EP0 to EP5 Data Register (EP0DT to EP5DT)
DBAPH
DMA Buffer Address Pointer
(DBAPH/DBAPM/DBAPL)
2
........ 445
OS
.......................... 374
............................ 261
...................................... 386
..................... 396
.............. 377
.......................... 242
.................................. 26
.................. 143, 150
...... 142
...... 142
................. 378
...................... 379
.................... 630
................................... 191
........................ 164
........................ 168
................................ 166
......................... 170
.................. 305
.............. 572
........... 295
..................... 100
DBAPL
DMA Buffer Address Pointer
(DBAPH/DBAPM/DBAPL)
DBAPM
DMA Buffer Address Pointer
(DBAPH/DBAPM/DBAPL)
DCSR
DMA Descriptor Channel Specification Register
..................................................90
(DCSR)
DCT
..............................................78
Data Counter (DCT)
DDCTH
About the Set Value of DMA Data Counter
(DDCTH/DDCTL)
DMA Data Counter (DDCTH/DDCTL)
DDCTL
About the Set Value of DMA Data Counter
(DDCTH/DDCTL)
DMA Data Counter (DDCTH/DDCTL)
DDR
Port Direction Register (DDR0 to DDRB)
DDWR
Configuration of DMA Descriptor Window Register
................................................95
(DDWR)
Dedicated Baud Rate Generator
Baud Rate of the External Clock Using the Dedicated
Baud Rate Generator
Baud Rate of the Internal Clock Using the Dedicated
Baud Rate Generator
Dedicated Register
...............................................32
Dedicated Registers
Delay Interruption
Notes on Use of Delay Interruption Generation Module
(Delay Interruption Request Latch)
Delay Interruption Generation Module
List of Register of Delay Interruption Generation Module
..........................................................110
Notes on Use of Delay Interruption Generation Module
(Delay Interruption Request Latch)
Delay Time
Sub Clock Oscillation Stabilization Delay Time
...............................................236
Function
Delayed Interrupt Generation Module
Block Diagram of Delayed Interrupt Generation
................................................110
Module
Operation of Delayed Interrupt Generation Module
Deleting Flash Memory
Method for Writing/deleting Flash Memory
Deletion
When Chip/sector Deletion Operates
DERH
DMA Permission Register (DERH/DERL)
DERL
DMA Permission Register (DERH/DERL)
Descriptor
Configuration of Extended Intelligent I/O Service
2
(EI OS) Descriptor (ISD)
INDEX
.....................100
.....................100
...................................96
......................96
...................................96
......................96
.................201
...............................502
...............................501
.............111
.............111
.....111
...............564
.......................572
..................94
..................94
...........................76
675