Timebase Timer Mode - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5.2

Timebase Timer Mode

The timebase timer mode terminates the original oscillation and all the operations other
than the timebase timer and the watch timer, resulting in termination of all the functions
other than the timebase timer and the watch timer.
Transition to Timebase Timer Mode
In the PLL clock mode or the main clock mode (the sub clock display bit (SCM)=1 of the clock selection
register (CKSCR)), writing "0" to the watch/timebase timer mode bit (TMD) of the low-power
consumption mode control register (LPMCR) makes the transition to the timebase timer mode.
Data retention function
In the timebase timer mode, the contents of dedicated registers such as accumulators and the internal RAM
are held unchanged.
Holding function
In the timebase timer mode, the external bus hold function is terminated, thereby neglecting a hold request
even a request is input. If a hold request is input during the transition to the timebase timer mode, the
condition of bus high-impedance is maintained and the HAK signal may not become "L".
Operation during an interrupt request
Writing "0" to the TMD bit of the low-power consumption mode control register (LPMCR) does not make
the transition to the timebase timer mode if there is an interrupt request.
Pin state
You can set whether the external pin in the timebase timer mode should be retained in the preceding state
or becomes to the high impedance state by controlling the pin state specification bit (SPL) in the LPMCR
register.
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