Ep0O Status Register (Ep0Os) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 13 USB FUNCTION
13.3.8

EP0O Status Register (EP0OS)

The EP0O status register (EP0OS) displays status related to transfer toward out for
EndPoint0.
EP0O Status Register (EP0OS)
Figure 13.3-10 shows the bit configuration of the EP0OS register (EP0OS).
Address bit 7
0000E4 Reserved
H
Address bit 15
0000E5 BFINI
H
1
1
R/W
The function of each bit in the EP0O status register (EP0OS) is described in the following.
[bit 15] BFINI: Reception buffer initialization bit
The forwarding data reception buffer is initialized. The BFINI bit is automatically set by setting the
RST bit in the UDC control register (UDCC). Consequently, when the reset operation has been
performed with the RST bit, clear the RST bit before clearing the BFINI bit.
BFINI
0
1
Note:
The initialization of the BFINI bit initializes a DRQO and the SPK bit. You must initialize the buffer
when you have set the STAL bit if necessary after you ensure that the DRQI or DRQO bit is set and
there is no access from the HOST.
288
Figure 13.3-10 EP0O Status Register (EP0OS)
6 5 4
X X X
X X X
R R R
14 13 12
DRQOIE SPKIE Reserved
0 0
Irrelevance Irrelevance
R/W R/W
Cancelling Initialization
Initialization of reception buffer
3 2 1
SIZE
X X X
X X X
R R R
11 10 9
Reserved DRQO SPK
0 0
0 0
R/W R/W
Operating mode
0
EP0O status register
←
X
Initial value
←
X
BFINI Reset
←
R
Access
8
Reserved
←
Initial value
←
BFINI Reset
←
Access