Error Status - Fujitsu F2MC-16LX Hardware Manual

14.5.8

Error Status

USB Mini-HOST supports various error information.
Error Status
Stuffing error
If continuous 6 bits happen to be "1", one bit of "0" should be inserted in somewhere in the sequence, but
the STUFF bit of the host error status register (HERR) is set to "1" as a stuffing error if continuous 7 bits of
"1" are detected. Please do "0" to the STUFF bit in the writing to clear this. If the next token is executed
without clearing the STUFF bit, it is updated at the termination of the next token.
Toggle error
When receiving an IN token, the TGERR bit in the host error register (HERR) is set to "1" if the toggle data
for the data packet and the TGGL bit of the host token endpoint register (HTOKEN) are compared and a
match is not detected. To clear the TGERR bit, write "0" to it of the host error register (HERR). If the next
token is executed without clearing the TGERR bit, it is updated at the termination of the next token.
CRC error
When receiving an IN token, data in the received data packet and CRC are calculated with the CRC
polynomial G(X)=X
happen and the CRC bit of the host error register (HERR) is set to "1". To clear the CRC bit, write "0" to it
of the host error register (HERR). If the next token is executed without clearing the CRC bit, it is updated
at the termination of the next token.
Time-out error
The TOUT bit of the host error status register (HERR) is set to "1" if a data packet or handshake is not
received in a given time, SE0 is detected in received data, or a stuffing error is detected. To clear the TOUT
bit, write "0" to it of the host error register (HERR). If the next token is executed without clearing the
TOUT bit, it is updated at the termination of the next token.
Receive error
If EP1 or EP2 is used as the reception buffer, the PKS bit of the EP1 control register (EP1C) or EP2 control
register (EP2C), respectively. If the received data is greater than that of the received packet size, the RERR
bit of the host error status register (HERR) is set to "1". To clear the RERR bit, write "0" to it of the host
error register (HERR). If the next token is executed without clearing the RERR bit, it is updated at the
termination of the next token.
16 15
+X +X2+1, and if the remainder is not (800D
CHAPTER 14 USB Mini-HOST
), then a CRC error is assumed to
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