Fujitsu F2MC-16LX Hardware Manual page 100

CHAPTER 3 INTERRUPT
Further, correction may be required, depending on the condition for executing EI
3.6-3.
Table 3.6-3 Compensation Value for Data Transfer at EI
I/O register address pointer
Buffer address Internal Access
pointer
External access
B: Byte data transfer
8: External bus width 8-bit/word transfer
Even: Word transfer at even address
Odd: Word transfer at odd address
At completion of counting by data counter (DCT) (for final data transfer)
Because a hardware interrupt is activated at the end of data transfer by EI
added. The EI
2
EI OS processing time when count ends =
2 OS processing time in data transfer + (21 + 6 × Z) machine cycles
EI
The interrupt handling time depends on the address to which the stack pointer points. Table 3.6-4 shows the
compensation values (Z) of the interrupt handling time.
Table 3.6-4 Compensation Value of Interrupt Handling Time (Z)
Address which stack pointer indicates
At the external 8 bits
At the external even number address
At the external odd number address
At the internal even number address
At the internal odd number address
84
B/Even
Odd
B/Even
8/Odd
2
OS processing time at the end of counting is calculated by the following expression.
2
OS Processing Time
Internal Access
B/Even Odd
0 + 2
+ 2 + 4
+ 1 + 3
+ 4 + 6
↑
Interrupt handling time
Compensation Value (Z)
+ 4
+ 1
+ 4
0
+ 2
2
OS, as shown in Table
External access
B/Even 8/Odd
+ 1 + 4
+ 3 + 6
+ 2 + 5
+ 5 + 8
2
OS, the interrupt handling time is