Fujitsu F2MC-16LX Hardware Manual page 626

APPENDIX
Table A-1 I/O Map (9/9)
Address
00790C
H
to
00790F
H
007910
Input Capture Data Register lower ch0
H
007911
Input Capture Data Register upper ch0
H
007912
Input Capture Data Register lower ch1
H
007913
Input Capture Data Register upper ch1
H
007914
Input Capture Data Register lower ch2
H
007915
Input Capture Data Register upper ch2
H
007916
Input Capture Data Register lower ch3
H
007917
Input Capture Data Register upper ch3
H
007918
Lower ch0 of output compare register
H
007919
Higher ch0 of output compare register
H
00791A
Lower ch1 of output compare register
H
00791B
Higher ch1 of output compare register
H
00791C
Lower ch2 of output compare register
H
00791D
Higher ch2 of output compare register
H
00791E
Lower ch3 of output compare register
H
00791F
Higher ch3 of output compare register
H
007920
DMA Buffer address pointer lower 8 bit
H
007921
DMA Buffer address pointer middle 8 bit
H
007922
DMA Buffer address pointer upper 8 bit
H
007923
DMA control register
H
DMA I/O Register Address Pointer lower 8
007924
H
bit
DMA I/O Register Address Pointer upper 8
007925
H
bit
007926
Lower 8 bits of DMA data counter
H
007927
Higher 8 bits of DMA data counter
H
007928
H
to
007FFF
H
• Explanation of reading/writing
R/W: Readable and Writable
R: Read only
W: Write only
• Explanation of initial value
0: The initial value is "0".
610
Registers Abbreviation Access
Use prohibited
R
IPCP0
R
R
IPCP1
R
R
IPCP2
R
R
IPCP3
R
R/W
OCCP0
R/W
R/W
OCCP1
R/W
R/W
OCCP2
R/W
R/W
OCCP3
R/W
DBAPL R/W
DBAPM R/W
DBAPH R/W
DMACS R/W
DIOAL R/W
DIOAH R/W
DDCTL R/W
DDCTH R/W
Use prohibited
Release Initial value
XXXXXXXX
XXXXXXXX
Input capture ch0/1
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Input capture ch2/3
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Output compare
ch0/1
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Output compare
ch2/3
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
µDMAC
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX