Each Register Of Extended Intelligent I/O Service; Os) Descriptor (Isd) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 3 INTERRUPT
3.6.2 Each Register of Extended Intelligent I/O Service (EI
Descriptor (ISD)
The extended intelligent I/O service (EI
registers.
• Data counter (DCT)
• I/O register address pointer (IOA)
2
• EI OS status register (ISCS)
• Buffer address pointer (BAP)
Note that resetting each register causes its initial value to be undefined.
Data Counter (DCT)
Data counter (DCT), a 16-bit length register, indicates the corresponding to the transfer data count. After
each of data has been transferred, the counter is decremented by 1 (reduced value). EI
counter reaches "0". Figure 3.6-3 shows the DCT configuration.
bit15 bit14 bit13
B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00
DCT
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W R/WR/WR/WR/W
: Readable/Writable
R/W
X : Indeterminate
I/O Register Address Pointer (IOA)
I/O register address pointer (IOA), a 16-bit length register, contains those low address (A15 to A0) of the
I/O register which are used for data transfer to or from the buffer. The upper address (A23 to A16)
containing all "0" data, can specify any I/O from 000000
configuration.
Figure 3.6-4 Configuration of I/O Register Address Pointer (IOA)
bit15 bit14 bit13
IOA
A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
: Readable/Writable
R/W
X
: Indeterminate
78
2
Figure 3.6-3 Configuration of Data Counter (DCT)
DCTH
bit9 bit8 bit7 bit6 bit5
bit12 bit11 bit10
IOAH
bit12 bit11 bit10 bit9 bit8
bit7 bit6 bit5
OS) descriptor (ISD) consists of the following
DCTL
bit4 bit3 bit2
to 00FFFF
H
IOAL
bit4 bit3 bit2
2
OS ends when this
Initial value
bit1 bit0
XXXXXXXXXXXXXXXX
. Figure 3.6-4 shows the IOA
H
Initial value
bit1 bit0
XXXXXXXXXXXXXXXX
2
OS)
B
B