Each Register Operation When Command Responds - Fujitsu F2MC-16LX Hardware Manual

16-bit microcontroller mb90330 series
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CHAPTER 13 USB FUNCTION
13.4.1

Each Register Operation when Command Responds

This section describes basic operations and control of registers and then how to
process USB packets (architecture). Firmware tasks triggered via CPU interrupt are
processed for each handshake operation. This is equivalent to processing each packet
on a per-stage basis.
Each Register Operation when Read Command Responds
For GetDescripter, SynchFrame, and the class vender command
Figure 13.4-4 Each Register Operation when Read Command Responds
Setup stage
Host PC
SET
Device
UP
Device
Host PC
DRQIIE
DRQI
DRQOIE
DRQO
SETP
Set-up processing
When the setup stage is received, DRQO is set. If the DRQO is set, CPU interrupt is raised and the SETP
flag is confirmed. It reads as many commands as necessary in the receive buffer if the DRQO is set (which
does not mean all eight bytes need to be read), decode the commands, performs setting tasks, and returns to
a point where a process was interrupted after it clears the SETP flag and DRQO interrupt cause.
Data stage processing
If the data stage indicates IN direction as a result of a decoded command, it enables the DRQIIE (as the
interrupt cause DRQI has the initial value of "1", it only sets an interrupt to be enabled), and transfers
transmission data to the transmission buffer triggered by an CPU interrupt. When transfer has been
completed, it clears the interrupt cause DRQI before returning to the interrupted point.
The DRQI is set when the data packet toward IN has been completed. The CPU interrupt is entered when
the DRQI is set, the transfer data is transferred to the transmission buffer to prepare for the next data
packet. When transfer has been completed. it clears the interrupt cause DRQI before returning to the
interrupted point.
300
DATA
IN
0
DATA
DATA0
ACK
write
Command
read
Next processing for
Setup
processing
data stage
Data stage
ACK
IN
ACK
DATA
DATA1
1
0
write
Soft clear
Soft clear
Status stage
DATA
OUT
1
ACK
DATA1
read
Command
completed
processing

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