State Transition Of Counter Operation - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 16 16-BIT RELOAD TIMER
16.3.1

State Transition of Counter Operation

The state transition of the counter operation is shown.
State Transition of Counter Operation
Reset
WAIT state
TIN pin: only trigger input
TOT pin: output value
of 16-bit reload register
16-bit timer register:
Retained the value at stop
the value is undefined until loading
immediately after reset.
External trigger of TIN
Status transition by Hardware
Status transition by Register access
WAIT WAIT signal (internal signal)
TRG Software trigger bit (TMCSR)
CNTE Timer counter enable bit (TMCSR)
UF Timer interrupt request flag bit (TMCSR)
RELD Reload operation enable bit (TMCSR)
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Figure 16.3-3 State Transition of Counter Operation
STOP state
TIN pin: input disabled
TOT pin: general-purpose I/O port
16-bit timer register:
Retained the value at stop
The value which is immediately
after reset is undefined.
CNTE = 0
CNTE = 1/TRG = 0
CNTE = 1, WAIT = 1
TRG = 1
(Software trigger)
LOAD
Load setting value of 16-bit reload
register to 16-bit timer register
CNTE = 0, WAIT = 1
CNTE = 1/TRG = 1
RUN state
TIN pin: function as input pin
UF = 1 &
TOT pin:
RELD = 0
(One-shot
mode)
16-bit timer register:
UF = 1 &
RELD = 1
(Reload mode)
CNTE = 1, WAIT = 0
CNTE = 0
CNTE = 1, WAIT = 0
of 16-bit reload timer
function as output pin
of 16-bit reload timer
Counter operation
TRG = 1
(Software trigger)
Load end