Fujitsu F2MC-16LX Hardware Manual page 309

[bit 11] BUSY: Busy flag bit
It indicates that writing into the transmission/receive buffer or accessing it for read from the HOST is
under way. The BUSY bit is set by the automatic operation, and reset.
BUSY
0
1
Note:
It indicates that the HOST is accessing a buffer that is different from either of the double buffer
accessed from CPU or DMA when the DRQ bit is set and the BUSY bit is set. Normally, you do not
need to control via the BUSY bit, but if you initialize the buffer with BFINI set, you must initialize the
buffer by setting the STAL bit after you ensure that the DRQ bit is set and the BUSY bit shows no
access from the HOST.
[bit 10] DRQ: Packet forwarding interrupt request bit
It indicates that the packet transfer for EP1 to EP5 has been successfully completed and data processing
is needed. The DRQ bit is a interrupt factor and writing "1" is ignored. Please clear by writing "0". "1"
is read at the read modification write.
DRQ
0
1
Note:
When the automatic buffer transfer mode (DMAE=1) is not used after the data read or write of
transmission and reception buffers is processed, "0" must be write to DRQ bit. When DRQ bit is
cleared, access buffer is switched. When the transfer direction is set to IN direction if DRQ bit is "1"
and the buffer is cleared without writing data, 0-byte data is set to it. In the initial setting, when the
DIR of the EP1 to EP5 control register (EP1C to EP5C) is set to "1", DRQ bit of the corresponding
end point is set at the same time. Furthermore, writing 0 is prohibited when DRQ bit is not set.
There is no access by HOST.
During writing/reading from HOST
Clearing Interrupt cause
The packet forwarding ends normally.
CHAPTER 13 USB FUNCTION
Operating mode
Operating mode
293