Dma Stop Status Register (Dssr) - Fujitsu F2MC-16LX Hardware Manual

3.8.2.3

DMA Stop Status Register (DSSR)

DMA stop status register (DSSR) indicates that the DMA transfer stopped due to the
STOP request.
The meaning of the bit in this register is different depending on the STP bit of the DMA
descriptor channel specification register (DCSR).
DMA Stop Status Register (DSSR)
Figure 3.8-4 Bit Configuration of DMA Stop Status Register (DSSR)
DCSR STP bit = 0
0000A4
STP15 STP14 STP13 STP12 STP11 STP10 STP9
H
R/W
DCSR STP bit = 1
0000A4
STP7
H
R/W
R/W : Readable/Writable
[bit15 to bit 0] STPx: DMA stop status
STPx bit
During DMA transfer, no STOP request is accepted from the resource.
0 [Initial value]
Please write "0" at STPx="0".
During DMA transfer, indicates that DMA transfer stopped in response to a STOP request from the
resource. However, "1" is not set to STPx bit even though the STOP request is accepted at last transfer.
1 If the SE bit of DMA control register is "1" and a STOP request is received by the associated channel,
the corresponding bit of the DMA permission register is cleared to "0".
When STPx = "1", writing "0" clears it to "0" and writing "1" holds the previous data.
The following two channels correspond to the STOP demand.
Bits other than STP10 and STP12 do not have the meaning.
Notes:
• DSSR is controlled by most significant bit (STP) of DCSR. If STP is "0", Bit 8 to Bit 15 will be
selected as being used for the DSSR. If it is "1", Bit 0 to Bit7 will be used for the DSSR. Because
the initial value of STP is "0", Bit 8 to Bit 15 is initially selected.
• To write data to the DSSR, use a read modify write (RMW) instruction.
7 6 5 4
R/W R/W R/W
7 6 5 4
STP6 STP5 STP4
R/W R/W R/W
Channel
ch10
ch12
3 2 1
R/W R/W R/W
3 2 1
STP3 STP2 STP1 STP0
R/W R/W R/W
Function
Corresponding STPx bit
STP10
STP12
CHAPTER 3 INTERRUPT
0
DSSR
STP8
R/W Initial value 00000000
0
DSSR
R/W Initial value 00000000
Resource
UART2/3, Reception
UART0/1, Reception
B
B
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