Iis Bus Controller - Samsung S5PV210 Hardware Design Manual

S5PV210_HARDWARE DESING GUIDE REV 1.0

25. IIS BUS CONTROLLER

25.1. Signal Description
Signal I/O
I2S_1_SCLK
I2S_1_CDCLK
I2S_1_LRCK
I2S_1_SDI
I2S_1_SDO
I2S_2_SCLK
I2S_2_CDCLK
I2S_2_LRCK
I2S_2_SDI
I2S_2_SDO
25.2. External Clock Source
S5PV210 provides a master clock to the codec through the Xi2sCDCLK line. This configuration has an advantage
that it is not necessary to configure oscillator circuit. For the making Master Clock, S5PV210 uses and divides
EPLL, MPLL or PCLK (refer to the User's Manual). If an oscillator circuit is configured for a precise clock for the
Sampling Frequency without PLLs or Internal clocks, there is a way to accept to this frequency as a source of
master clock through the Xi2sCDCLK line.
S5PV210 can supply 24MHz clock to Codec chip via CLKOUT line.(refer to the User's Manual). Even at Power
down mode, this signal keep supplying to Codec chip. When Codec chip need 24MHz, external oscillator circuit can
be reduced by using this configuration.
Description
IO IIS-bus serial clock for channel 1
IO IIS CODEC system clock for channel 1
IO IIS-bus channel select clock for channel 1
I IIS-bus serial data input for channel 1
O IIS-bus serial data output for channel 1
IIS-bus serial clock for channel 2
IO
IO IIS CODEC system clock for channel 2
IO IIS-bus channel select clock for channel 2
I IIS-bus serial data input for channel 2
O IIS-bus serial data output for channel 2
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