Nand Flash Controller - Samsung S5PV210 Hardware Design Manual

S5PV210_HARDWARE DESING GUIDE REV 1.0

8. NAND Flash Controller

8.1. Signal Description
Signal I/O
O
NF_CLE
O
NF_ALE
O
NF_FWEn
O
NF_FREn
I
NF_RnB[3:0]
XM0DATA[15:0] IO
Xm0nCS[2] /
O
NFCSn[0]
Xm0nCS[3] /
O
NFCSn[1]
Xm0nCS[4] /
O
NFCSn[2]
Xm0nCS[5] /
O
NFCSn[3]
Xm0nCS2, Xm0nCS3, Xm0nCS4, Xm0nCS5 can be used for NAND device. Some large capacity NAND flash have
two or more nCE signal.
Description
Memory Port 0 NAND Command Latch Enable
Memory Port 0 NAND Address Latch Enable
Memory Port 0 NAND Flash Write Enable
Memory Port 0 NAND Flash Read Enalbe
Memory Port 0 NAND Flash Ready/Busy
Memory port 0 Data bus
Memory Port 0 NAND Chip Select0
Memory Port 0 NAND Chip Select1
Memory Port 0 NAND Chip Select2
Memory Port 0 NAND Chip Select3
Comment
- NF_RnB[0] signal used for iROM
boot
- 4.7Kohm external pull-up
- Used for iROM boot
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