Hardware Interrupts; Structure Of Hardware Interrupt - Fujitsu F2MCTM-16LX Hardware Manual

3.5

Hardware Interrupts

In response to an interrupt request signal from an internal resource, the CPU pauses
current program execution and transfers control to the interrupt processing program
defined by the user. This function is called the hardware interrupt function.
Hardware Interrupts
A hardware interrupt occurs when the relevant conditions are satisfied as a result of two operations:
comparison between the interrupt request level and the value in the interrupt level mask register (ILM) of
PS in the CPU, and hardware reference to the I flag value of PS.
The CPU performs the following processing when a hardware interrupt occurs:
• Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system
stack.
• Sets ILM in the PS register. The currently requested interrupt level is automatically set.
• Fetches the corresponding interrupt vector value and branches to the processing indicated by that value.

Structure of Hardware Interrupt

Hardware interrupts are handled by the following 3 sections:
Internal resources
Interrupt enable and request bits: Used to control interrupt requests from resources.
Interrupt controller
ICR: Assigns interrupt levels and determines the priority levels of simultaneously requested interrupts.
CPU
I and ILM: Used to compare the requested and current interrupt levels and to identify the interrupt enable
status.
Microcode: Interrupt processing step
The status of these sections are indicated by the resource control registers for internal resources, the ICR
for the interrupt controller, and the CCR value for the CPU. To use a hardware interrupt, set the three
sections beforehand by using software.
The interrupt vector table referred during interrupt processing is assigned to addresses FFFC00
FFFFFF
H
"Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers" in "APPENDIX D List of
Interrupt Vectors" shows the assignment of the MB90360 series.
in memory. These addresses are shared with software interrupts.
CHAPTER 3 INTERRUPTS
to
H
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