Bit Timing Register (Btr) - Fujitsu F2MCTM-16LX Hardware Manual

CHAPTER 21 CAN CONTROLLER
21.4.7

Bit Timing Register (BTR)

Bit timing register (BTR) sets the prescaler and bit timing setting.
Register Configuration
Address
CAN1: 007D07
Address
CAN1: 007D06
R/W : Read/Write
X : Undefined
− :
Unused
Register Function
Table 21.4-6 Function of Each Bit of the Bit Timing Register (BTR)
Bit Name
bit14 TS2.2 to TS2.0:
to Time segment 2
bit12 setting bits 2 to 0
bit11 TS1.3 to TS1.0:
to Time segment 1
bit8 setting bits 3 to 0
bit7 RSJ1, RSJ0:
bit6 Resynchronization
jump width setting
bits 1, 0
bit5 PSC5 to PSC0:
to Prescaler setting bits
bit0 5 to 0
Note: Please set (CSR: HALT=1) to bit timing register (BTR) after stopping the bus operation. Please release the bus
operation stop by writing "0" in the HALT bit of the control status register after the setting of bit timing register
(BTR) is ended.
462
Figure 21.4-6 Configuration of the Bit Timing Register (BTR)
bit15 bit14 bit13
−
TS2.2 TS2.1
H
−
R/W R/W
bit7 bit6 bit5
RSJ1 RSJ0 PSC5
H
R/W R/W R/W
These bits define the number of the time quanta (TQ's) for the time segment 2 (TSEG2).
The time segment 2 is equal to the phase buffer segment 2 (PHASE_SEG2) in the CAN
specification.
These bits define the number of the time quanta (TQ's) for the time segment 1 (TSEG1).
The time segment 1 is equal to the propagation segment (PROP_SEG) + phase buffer
segment 1 (PHASE_SEG1) in the CAN specification.
These bits define the number of the time quanta (TQ's) for the resynchronization jump
width.
These bits define the time quanta (TQ) of the CAN controller. (see below for details.)
bit12 bit11 bit10
TS2.0 TS1.3 TS1.2 TS1.1
R/W R/W R/W
bit4 bit3 bit2
PSC4 PSC3 PSC2 PSC1
R/W R/W R/W
Function
bit9 bit8 BTR1(Upper)
TS1.0 Reset value
X1 1 1 1 1 1 1
R/W R/W
bit1 bit0 BTR1(Lower)
PSC0 Reset value
11 1 1 1 1 1 1
R/W R/W
B
B