Resets - Fujitsu F2MCTM-16LX Hardware Manual

CHAPTER 7 RESETS
7.1

Resets

If a reset is generated, the CPU immediately stops the current execution process and
waits for the reset to be cleared. The CPU then begins processing at the address
indicated by the reset vector.
The four causes of a reset are as follows
• Power-on reset
• External reset request via the RST pin
• Software reset request
• Watchdog timer overflow
• Low voltage detection reset request (product with "T"-suffix)
• CPU operation detection reset request (product with "T"-suffix)
• Clock supervisor reset request (MB90367/T(S))
Causes of a Reset
Table 7.1-1 lists the causes of a reset.
Table 7.1-1 Cause of a Reset
Reset
Power-on At power on
External pin L level input to RST pin
Software Write "0" to internal reset signal
generation bit (RST) of low-power
consumption mode control register
(LPMCR)
Watchdog timer Watchdog timer overflow
When low voltage (4.0 V ± 0.3 V) is
Low voltage
detection reset detected
(with "T"-suffix)
CPU operation When CPU operation detection
detection reset counter overflows
(with "T"-suffix)
Clock supervisor When failure of main clock/subclock is
reset detected
MCLK: Main clock (oscillation clock frequency divided by 2)
Power-on reset
A power-on reset is generated when the power is turned on. The oscillation stabilization wait times is fixed
16
to 2 oscillation clock cycles (2
120
Cause
Main clock (MCLK)
Main clock (MCLK)
Main clock (MCLK)
Main clock (MCLK)
Main clock (MCLK)
Main clock (MCLK)
Internal CR
oscillation clock
16
/HCLK) (approx. 16.38 ms, oscillating at 4 MHz). When the oscillation
Machine clock Watchdog
timer
Stop
Oscillation
stabilization wait
Stop Yes
Stop None
Stop None
Stop None
Stop None
Stop None
None