Fujitsu F2MCTM-16LX Hardware Manual page 611

Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles
Operand
Internal register
Internal memory
Even address
Internal memory
Odd address
*2
External data bus
16-bit even address
*2
External data bus
16-bit odd address
*2
External data bus
8-bits
*1: (b), (c), and (d) are used for
Instruction List".
*2: When an external data bus is used, the number of cycles during which an instruction is made to wait
by ready - signal input or automatic ready must also be added.
Note:
When an external data bus is used, the cycle counts during which an instruction is made to wait by
ready input or automatic ready must also be added.
Table B.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles
Instruction
Internal memory
External data bus 16-bits
External data bus 8-bits
Note:
• When an external data bus is used, the cycle counts during which an instruction is made to wait by
ready input or automatic ready must also be added.
• Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the correction
values to calculate the worst case.
*1
(b) byte
Cycle Access
count count
+0 1
+0 1
+0 1
+1 1
+1 1
+1 1
(cycle count) and B (correction value) in "B.8 F
Byte boundary
APPENDIX B Instructions
*1
(c) word
Cycle Access Cycle
count count count
+0 1
+0 1
+2 2
+1 1
+4 2
+4 2
2
MC-16LX
Word boundary
- +2
- +3
+3 -
*1
(d) long
Access
count
+0 2
+0 2
+4 4
+2 2
+8 4
+8 4
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