Precautions For Use Of "Div A, Ri" And "Divw A, Rwi" Instructions - Fujitsu F2MCTM-16LX Hardware Manual

CHAPTER 2 CPU
2.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi"
Instructions
Set "00 " in the bank register before using the "DIV A, Ri" and "DIVW A, RWi"
H
instructions.

Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions

Table 2.11-1 Precautions for Use of "DIVA,Ri" and "DIVWA,RWi" Instructions (i=0 to 7)
Bank register name affected
Instruction by the execution of the
instructions listed on the left
DIVA,R0
DIVA,R1
DIVA,R4
DIVA,R5
DIVWA,RW0
DIVWA,RW1
DIVWA,RW4
DIVWA,RW5
DIVA,R2
DIVA,R6
DIVWA,RW2
DIVWA,RW6
DIVA,R3
DIVA,R7
USB, SSB
DIVWA,RW3
DIVWA,RW7
*1: Depends on the S bit of the CCR register
*2: In the event that S bit of the CCR register is 0
If the value of the bank registers (DTB, ADB, USB, and SSB) is "00
stored in the register of the instruction operands. Otherwise, the upper eight bits is specified by the bank
register corresponding to the register of the instruction operand, and the lower 16 bits is the same as the
address of the register of the instruction operand. The remainder is stored in the bank register specified by
the upper eight bits.
52
(DTB: Upper 8 bits)+(0180
(DTB: Upper 8 bits)+(0180
(DTB: Upper 8 bits)+(0180
(DTB: Upper 8 bits)+(0180
DTB
(DTB: Upper 8 bits)+(0180
(DTB: Upper 8 bits)+(0180
(DTB: Upper 8 bits)+(0180
(DTB: Upper 8 bits)+(0180
(ADB: Upper 8 bits)+(0180
(ADB: Upper 8 bits)+(0180
ADB
(ADB: Upper 8 bits)+(0180
(ADB: Upper 8 bits)+(0180
*2
(USB : Upper 8 bits)+(0180
*2
(USB : Upper 8 bits)+(0180
*1
*2
(USB : Upper 8 bits)+(0180
*2
(USB : Upper 8 bits)+(0180
Address that stores the remainder
+RP × 10
+8
H H H
+RP × 10
+9
H H H
+RP × 10
+C
H H H
+RP × 10
+D
H H H
+RP × 10
+0
H H H
+RP × 10
+2
H H H
+RP × 10
+8
H H H
+RP × 10
+A
H H H
+RP × 10
+A
H H H
+RP × 10
+E
H H H
+RP × 10
+4
H H H
+RP × 10
+E
H H H
+RP × 10
+B
H H
+RP × 10
+F
H H
+RP × 10
+6
H H
+RP × 10
+E
H H
", the remainder after division is
H
Lower 16 bits)
Lower 16 bits)
Lower 16 bits)
Lower 16 bits)
Lower 16 bits)
Lower 16 bits)
Lower 16 bits)
Lower 16 bits)
Lower 16 bits)
Lower 16 bits)
Lower 16 bits)
Lower 16 bits)
Lower 16 bits)
H
Lower 16 bits)
H
Lower 16 bits)
H
Lower 16 bits)
H