Fujitsu F2MC-8L MB89626 Manuals

Manuals and User Guides for Fujitsu F2MC-8L MB89626. We have 1 Fujitsu F2MC-8L MB89626 manual available for free PDF download: Hardware Manual

Fujitsu F2MC-8L MB89626 Hardware Manual

Fujitsu F2MC-8L MB89626 Hardware Manual (354 pages)

8-BIT MICROCONTROLLER

Brand: Fujitsu | Category: Microcontrollers | Size: 2.24 MB

Table of Contents

Figures

12
- Table of Contents
  12
Cpu/Chapter 4 I\/O Ports

21
Cpu

52
- Chapter 3 Cpu
  
  52
I\/O Ports

108
-Bit Pwm Timer

158
- Overview of 8-Bit PWM Timer
  159
- Chapter 7 8-Bit Pwm Timer
  
  160
Pulse Width Count Timer (Pwc)

178
- Overview of Pulse Width Count Timer
  179
- Chapter 8 Pulse Width Count Timer (Pwc)
  
  181
-Bit Timer/Counter

200
- Overview of 16-Bit Timer/Counter
  201
- Chapter 9 16-Bit Timer/Counter
  
  203
-Bit Serial I\/O (Serial I/O-1 and Serial I/O-2)

218
- Overview of 8-Bit Serial I/O
  219
- Chapter 10 8-Bit Serial I/O (Serial I/O-1 and Serial I/O-2)
  
  221
Buzzer Output

246
- Overview of Buzzer Output
  247
- Chapter 11 Buzzer Output
  
  248
External Interrupt Circuit (Edge)

252
- Overview of External Interrupt Circuit
  253
- Chapter 12 External Interrupt Circuit (Edge)
  
  254
A/D Converter

264
- Overview of A/D Converter
  265
- Chapter 13 A/D Converter
  
  267
Clock Monitor Function

284
- Overview of Clock Monitor Function
  285
- Chapter 14 Clock Monitor Function
  
  286
  - Figure 14.2 Block Diagram of Clock Monitor Function
    286
    
    Block Diagram of Clock Monitor Function
    286
    
    Figure 14.3 Block Diagram of P30/ADST/CLKO Pin
    287
    
    Structure of Clock Monitor Function
    287
    
    Figure 14.4 Clock Output Control Register (CLKE)
    288
    
    Clock Output Control Register (CLKE)
    288
- Appendix
  
  295
  - Figure B.1A Direct Addressing
    295
  - Figure B.1B Extended Addressing
    295
  - Figure B.1C Bit Direct Addressing
    295
  - Figure B.1D Index Addressing
    296
  - Figure B.1E Pointer Addressing
    296
  - Figure B.1F General-Purpose Register Addressing
    296
  - Figure B.1G Immediate Addressing
    296
  - Figure B.1H Vector Addressing
    297
  - Figure B.1I Relative Addressing
    297
  - Figure B.1J Inherent Addressing
    297
  - Figure B.2A JMP @A
    298
  - Figure B.2B MOVW A, PC
    298
  - Figure B.2C MULU a
    298
  - Figure B.2D DIVU a
    299
  - Figure B.2E XCHW A,PC
    299
  - Figure B.2F Example Using XCHW A,PC
    299
  - Figure B.2G Execution Example of CALLV #3
    300
  - Figure da Memory Map in EPROM Mode (MB89P625)
    310
  - Figure Db Memory Map in EPROM Mode (MB89P627, MB89P629)
    310
  - Figure DC Screening Procedure
    314
  - Figure D.2 Memory Map of Piggyback/Evaluation Device
    316

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