Fujitsu F2MCTM-16LX Hardware Manual page 587

Table A-1 I/O Map (4/5)
Address
00009F
Delayed interrupt/release register
H
0000A0
Low-power mode control register
H
0000A1
Clock selection register
H
0000A2 to
H
Reserved
0000A7
H
0000A8
Watchdog timer control register
H
0000A9
Time base timer control register
H
0000AA
Watch timer control register
H
0000AB to
H
Reserved
0000AD
H
Flash control status
0000AE
H
(Flash device only.)
0000AF
Reserved
H
0000B0
Interrupt control register 00
H
0000B1
Interrupt control register 01
H
0000B2
Interrupt control register 02
H
0000B3
Interrupt control register 03
H
0000B4
Interrupt control register 04
H
0000B5
Interrupt control register 05
H
0000B6
Interrupt control register 06
H
0000B7
Interrupt control register 07
H
0000B8
Interrupt control register 08
H
0000B9
Interrupt control register 09
H
0000BA
Interrupt control register 10
H
0000BB
Interrupt control register 11
H
0000BC
Interrupt control register 12
H
0000BD
Interrupt control register 13
H
0000BE
Interrupt control register 14
H
0000BF
Interrupt control register 15
H
0000C0 to
H
Reserved
0000C9
H
Register Abbreviation
DIRR
LPMCR
CKSCR
WDTC
TBTC
WTC
FMCS
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
Access Peripheral
Delayed Interrupt
R/W
Generation Module
Low Power
W, R/W
Controller
Low Power
R, R/W
Controller
R, W Watchdog Timer
W, R/W Time Base Timer
R, R/W Watch Timer
R, R/W Flash Memory
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
Interrupt Controller
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
APPENDIX A I/O Maps
Initial value
XXXXXXX0
B
0 0 0 1 1 0 0 0
B
1 1 1 1 1 1 0 0
B
XXXXX111
B
1 XX 0 0 1 0 0
B
1 X 0 0 1 0 0 0
B
0 0 0 X 0 0 0 0
B
0 0 0 0 0 1 1 1
B
0 0 0 0 0 1 1 1
B
0 0 0 0 0 1 1 1
B
0 0 0 0 0 1 1 1
B
0 0 0 0 0 1 1 1
B
0 0 0 0 0 1 1 1
B
0 0 0 0 0 1 1 1
B
0 0 0 0 0 1 1 1
B
0 0 0 0 0 1 1 1
B
0 0 0 0 0 1 1 1
B
0 0 0 0 0 1 1 1
B
0 0 0 0 0 1 1 1
B
0 0 0 0 0 1 1 1
B
0 0 0 0 0 1 1 1
B
0 0 0 0 0 1 1 1
B
0 0 0 0 0 1 1 1
B
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