Fujitsu F2MCTM-16LX Hardware Manual page 670

INDEX
Data Polling Flag
Data Polling Flag (DQ7) ................................... 541
Data Read
Data Read by Read Access................................ 636
Data Register
List of Message Buffer (data register)................. 451
List of Message Buffers
(DLC registers and Data registers) ........ 450
DCT
Data Counter (DCT) ........................................... 76
DDR
Port Direction Register (DDR)........................... 172
Delayed Interrupt Generation Module
Block Diagram of Delayed Interrupt Generation
Module................................................. 85
Explanation of Operation of Delayed Interrupt
Generation Module................................ 88
Overview of Delayed Interrupt Generation Module
............................................................ 84
Precautions when Using Delayed Interrupt Generation
Module................................................. 89
Program Example of Delayed Interrupt Generation
Module................................................. 90
Delayed Interrupt Request Generate/cancel Register
Delayed Interrupt Request Generate/cancel Register
(DIRR)................................................. 87
Descriptor
Extended Intelligent I/O Service Descriptor (ISD)
............................................................ 76
Detailed Explanation
Detailed Explanation of Flash Memory Write/erase
.......................................................... 544
Detect Address
Setting Detect Address......................................516
Detect Address Setting Registers
Detect Address Setting Registers (PADR0 to PADR5)
.......................................................... 513
Functions of Detect Address Setting Registers
.......................................................... 514
Detection Level Setting Register
Detection Level Setting Register (ELVR1) ......... 323
Device
Handling the Device ........................................... 21
Direct Addressing
Direct Addressing............................................. 580
Direct Pin Access
LIN-UART Direct Pin Access ........................... 432
DIRR
Delayed Interrupt Request Generate/cancel Register
(DIRR)................................................. 87
DIV
Precautions for Use of "DIV A,Ri" and
"DIVW A,RWi" Instructions .................. 52
654
Use of the "DIV A,Ri" and "DIVW A,RWi"
Instructions without Precautions ............ 53
DIVW
Precautions for Use of "DIV A,Ri" and
"DIVW A,RWi" Instructions.................. 52
Use of the "DIV A,Ri" and "DIVW A,RWi"
Instructions without Precautions ............ 53
DLC Registers
List of Message Buffers
(DLC Registers and Data registers)....... 450
DQ5
Timing Limit Exceeded Flag (DQ5) .................. 543
DQ6
Toggle Bit Flag (DQ6) ..................................... 542
DQ7
Data Polling Flag (DQ7)................................... 541
DTP
DTP Function .................................................. 332
Program Example of DTP Function ................... 336
DTP/External Interrupt
Block Diagram of DTP/External Interrupt .......... 315
DTP/External Interrupt Function ....................... 314
DTP/External Interrupt Operation...................... 329
List of Registers and Reset Values in DTP/
External Interrupt................................ 318
Pins of DTP/External Interrupt .......................... 317
Precautions when Using DTP/External Interrupt
......................................................... 333
Program Example of DTP/External Interrupt Function
......................................................... 335
Setting of DTP/External Interrupt ...................... 327
DTP/External Interrupt Enable Register
DTP/External Interrupt Enable Register (ENIR1)
......................................................... 321
DTP/External Interrupt Factor Register
DTP/External Interrupt Factor Register (EIRR1)
......................................................... 319
E
2
E PROM
2
PROM Memory Map.................................... 518
E
Operation of Address Match Detection Function at
Storing Patch Program in E
System Configuration and E
......................................................... 517
ECCR
Extended Communication Control Register (ECCR)
......................................................... 403
Effective Address
Effective Address Field ............................ 579, 596
2
EI OS
16-bit I/O Timer Interrupt and EI
8-/10-bit A/D Converter Interrupt and EI
2
Conversion Using EI OS .................................. 366
2
PROM ...... 520
2
PROM Memory Map
2
OS................. 228
2
OS...... 358