Fujitsu F2MCTM-16LX Hardware Manual page 325

Output waveform in 8+8-bit PPG output operation mode
The High and Low pulse widths to be outputted are determined by adding 1 to the value in the PPG reload
register and multiplying it by the count clock cycle.
The equations for calculating the pulse width are shown below:
PL=T × (Ln+1) × (Lm+1)
PH=T × (Hn+1) × (Hm+1)
PL: Low width of output pulse of PPGm pin
PH: High width of output pulse of PPGm pin
L : Values of 8 bits in PPG reload register (PRLLn)
n
H : Values of 8 bits in PPG reload register (PRLHn)
n
L : Values of 8 bits in PPG reload register (PRLLm)
m
H : Values of 8 bits in PPG reload register (PRLHm)
m
T: Count clock cycle
Figure 16.5-7 shows the output waveform in the 8+8-bit PPG output operation mode.
Figure 16.5-7 Output Waveform in 8+8-bit PPG Output Operation Mode
Operation start
PPG operation enable
bit (PENn, PENm)
PPGn output pin
PPGm output pin
Ln : Values of 8 bits in PPG reload register (PRLLn)
Hn : Values of 8 bits in PPG reload register (PRLHn)
Hm : Values of 8 bits in PPG reload register (PRLLm)
Lm : Values of 8 bits in PPG reload register (PRLHm)
T : Count clock cycle
Note: n = C, E
m = n + 1
T × (L + 1) T × (H + 1)
0 0
T × (L + 1) × (L + 1)
0 1
CHAPTER 16 8-/16-BIT PPG TIMER
Operation stop
T × (H + 1) × (H + 1)
0 1
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