Fujitsu F2MCTM-16LX Hardware Manual page 496

CHAPTER 21 CAN CONTROLLER
Figure 21.4-23 Configuration of the Acceptance Mask Register 1 (AMR1)
Address
CAN1: 007D18
Address
CAN1: 007D19
Address
CAN1: 007D1A
Address
CAN1: 007D1B
R/W : Read/Write
X : Undefined
−
: Unused
: Used bit in typical frame format
Register Function
0: Compare
Compare the bit (be set to "0") of the acceptance code (ID register IDRx for comparing with the received
message ID) corresponding to this bit with the bit of the received message ID. If there is no match, no
message is received.
1: Mask
Mask the bit of the acceptance code ID register (IDRx) corresponding to this bit. No comparison is made
with the bit of the received message ID.
Notes:
• AMR0 and AMR1 should be set when all the message buffers (x) selecting AMR0 and AMR1 are
invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffers are valid
(BVALx = 1) may cause unnecessary received messages to be stored.
• To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while the CAN controller is
operating for CAN communication (the read value of the CSR: HALT bit is 0 and the CAN controller is
operating for CAN bus communication to enable transmission and reception), follow the procedure in
"21.13 Precautions when Using CAN Controller".
480
bit7 bit6 bit5
AM28 AM27 AM26
H
R/W R/W R/W
bit15 bit14 bit13
AM20 AM19 AM18
H
R/W R/W R/W
bit7 bit6 bit5
AM12 AM11 AM10
H
R/W R/W R/W
bit15 bit14 bit13
AM4 AM3 AM2
H
R/W R/W R/W
bit4 bit3 bit2
AM25 AM24 AM23 AM22
R/W R/W R/W
bit12 bit11 bit10
AM17 AM16 AM15 AM14
R/W R/W R/W
bit4 bit3 bit2
AM9 AM8 AM7
R/W R/W R/W
bit12 bit11 bit10
−
AM1 AM0
−
R/W R/W
bit1 bit0 AMR11(Byte0)
AM21 Reset value
XXXXXXXX
R/W R/W
bit9 bit8 AMR11(Byte1)
AM13 Reset value
XXXXXXXX
R/W R/W
bit1 bit0 AMR11(Byte2)
AM6 AM5 Reset value
XXXXXXXX
R/W R/W
bit9 bit8 AMR11(Byte3)
− −
Reset value
XXXXXXXX
− −
B
B
B
B