Explanation Of Operation Of 16-Bit Free-Run Timer - Fujitsu F2MCTM-16LX Hardware Manual

13.5

Explanation of Operation of 16-bit Free-run Timer

After a reset, the 16-bit free-run timer starts incrementing from "0000
value of the 16-bit free-run timer is the base time of the input capture.
Explanation of Operation of 16-bit Free-run Timer
Operation of the 16-bit free-run timer requires the setting shown in Figure 13.5-1 .
TCCSH/TCCSL
TCDT
: Used bit
: Undefined bit
0 : Setting to "0"
[Setting of counter value in 16-bit free-run timer]
• Because the timer operation is enabled (TCCSL:STOP=0) after a reset, the 16-bit free-run timer starts
incrementing from the counter value "0000
• When setting the counter value of the 16-bit free-run timer, disable the operation of the 16-bit free-run
timer (TCCSL:STOP=1), set the value that starts counting to the timer data register, enable the timer
operation (TCCSL:STOP=0).
[Generation of overflow and interrupt request]
• When overflow ("FFFF
flag is set to "1" (TCCSL:IVF) and starts incrementing from "0000
• When the timer overflow interrupt request is enabled (TCCSL:IVFE=1), the interrupt request is
occurred.
[Clear factor of counter value and clear timing]
Table 13.5-1 shows the clear factor and clear timing of the 16-bit free-run timer.
Table 13.5-1 Clear Factor of Counter Value and Clear Timing
Clear factor
When "1" to timer clear bit of timer control status register (TCCSL:
CLR)
Write "0000 " to timer data register during stopping
H
Reset
Timer overflow
Figure 13.5-1 Setting of 16-bit Free-run Timer
bit15 14 13 12 11
ECKE
Counter value of 16-bit free-run timer
" → "0000
H
10 9 bit8 bit7 6
IVF IVFE
STOP
0
".
H
") occurs in the 16-bit free-run timer, the timer overflow generation
H
Clear timing
Synchronize with generation of factor
Synchronize with generation of factor
Synchronize with generation of factor
Synchronize with count timing
CHAPTER 13 16-Bit I/O TIMER
". The counter
H
5 4 3 2 1 bit0
CLR CLK2 CLK1 CLK0
0
0
".
H
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