Ppgd Operation Mode Control Register (Ppgcd) - Fujitsu F2MCTM-16LX Hardware Manual

CHAPTER 16 8-/16-BIT PPG TIMER
16.3.2

PPGD Operation Mode Control Register (PPGCD)

The PPGD operation mode control register provides the following settings about
operation of 8-/16-bit PPG timer D:
• Enabling or disabling operation of 8-/16-bit PPG timer D
• Switching between pin functions (enabling or disabling pulse output)
• Enabling or disabling underflow interrupt
• Setting underflow interrupt request flag
• Setting the operation mode of the 8-/16-bit PPG timer D and C
This section explains the PPGCD function only. The PPGCF has the same function as
the PPGCD, and the 8-/16-bit PPG timer F is set.
PPGD Operation Mode Control Register (PPGCD)
Figure 16.3-3 PPGD Operation Mode Control Register (PPGCD)
Address:
chD PPGCD 000049
Other channel:
chF PPGCF 00004D
R/W : Read/Write
W : Write only
X : Indeterminate
−
: Undefined
: Reset value
294
15 14 13 12 11
H
PEN1 PE1 PIE1 PUF1 MD1 MD0
−
R/W R/W R/W R/W
H
10 9 8
Reset value
Re-
0 X 0 0 0 0 0 1
served
bit 8
R/W R/W W
Re-
served
1
Always set to "1".
bit 10 bit 9
MD1 MD0
0 0
0 1
1 0
1 1
bit 11
PUF1
Read
0
No underflow
1
Underflow
bit 12
PIE1
0
Underflow interrupt request disable
1
Underflow interrupt request enable
bit 13
PE1
General-purpose I/O port (pulse output
0
disable)
1
PPG1 output (pulse output enable)
bit 15
PEN1
0
Counting disable (holds "L" level output)
1
Counting enable
B
Reserved bit
Operation mode select bits
8-bit PPG output 2 channels
independent operation mode
8+8-bit PPG output operation
mode
Setting disable
16-bit PPG output operation mode
Underflow generation flag bit
Write
Clears PUF1 bit
No effect
Underflow interrupt enable bit
PPG1 pin output enable bit
PPG1 operation enable bit