Fujitsu F2MCTM-16LX Hardware Manual page 290

CHAPTER 15 WATCH TIMER
Table 15.3-1 Functions of Watch Timer Control Register (WTC)
Bit Name
bit7 WDCS:
Watchdog clock select bit
bit6 SCE:
Oscillation stabilization wait
time end bit
bit5 WTIE:
Overflow interrupt enable bit
bit4 WTOF:
Overflow flag bit
bit3 WTR:
Watch timer clear bit
bit2 WTC2, WTC1, WTC0:
to Interval time select bits
bit0
274
This bit selects the operation clock of the watchdog timer.
<Main clock mode or PLL clock mode>
When set to "0": Selects output of watch timer as operation clock of watchdog timer.
When set to "1": Selects output of timebase timer as operation clock of watchdog timer.
<Subclock mode>
Always set this bit to 0 to select the output of the watch timer.
Note:
The watch timer and the timebase timer operate asynchronously. When the WDCS bit is
changed from 0 to 1, the watchdog timer may run fast. The watchdog timer must be
cleared before and after changing the WDCS bit.
This bit indicates that the oscillation stabilization wait time of the subclock ends.
When cleared to "0": Subclock in oscillation stabilization wait state
When set to "1" : Subclock oscillation stabilization wait time ends
• The oscillation stabilization wait time of the subclock is fixed at 2
subclock frequency).
This bit enables or disables generation of an interrupt request when the watch timer counter
overflows (carries).
When set to "0": Interrupt request not generated even at overflow (WTOF=1)
When set to "1": Interrupt request generated at overflow (WTOF = 1)
This bit is set to "1" when the counter value of the watch timer reaches the value set by the
interval time select bit.
When an overflow carry occurs (WTOF = 1) with interrupt request enabled (WTIE = 1), an
interrupt request is generated.
When set to "0": Clears watch timer counter
When set to "1": No effect
• The overflow flag bit is set to "1" when the bit of the watch timer counter corresponding
to the interval time set by the interval time select bits (WTC2 to WTC0) overflows (car-
ries).
This bit clears the watch timer counter.
When set to "0": Clears watch timer counter to "0000
When set to "1": No effect
Read: 1 is always read.
These bits set the interval time of the watch timer.
• When the interval time set by the WTC2 to WTC0 bits is reached, the corresponding bit
of the watch timer counter overflows (carries) and the overflow flag bit is set
(WTC:WTOF = 1).
• To set the WTC2 to WTC0 bits, set the WTOF bit to 0.
Function
14
".
H
/SCLK (SCLK: