Fujitsu F2MCTM-16LX Hardware Manual page 653

Write, Data Polling, Read (WE control)
3rd bus cycle
FxAAAA
AQ18 to AQ0
CE
OE
t
GHWL
WE
DQ7 to DQ0
PA : Write address
PD : Write data
DQ : Reverse output of write data
7
D : Output of write data
OUT
Note:
• Describes the last 2-bus cycle of 4-bus cycle sequences.
• "Fx" in "FxAAAA" described as address is any of FF.
Figure C-2 Write, Data Polling, Read (WE control)
PA
H
t t
WC AH
t t
CH
CS
t
WP
t
WPH
t
t
DS
DH
A0
PD
H
APPENDIX C Timing Diagrams in Flash Memory Mode
Data polling
PA
t
WHWH1
t
DQ7 D
OUT
t
RC
t
CE
t
OE
DF t
OH
D
OUT
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