Fujitsu F2MCTM-16LX Hardware Manual page 138

CHAPTER 7 RESETS
CPU operation detection reset
The CPU operation detection reset is 20-bit counter that the source oscillation is count-locked. If the CL bit
of the low voltage/CPU operation detection reset is not cleared within a specified time after activation, the
reset is generated.
The oscillation stabilization wait time is not required for the CPU operation detection reset.
Clock supervisor reset
When the failure of the main clock/subclock is detected, the clock supervisor reset is generated.
The oscillation stabilization wait time is not required for the clock supervisor reset.
Definition of clocks
HCLK: Oscillation clock frequency
MCLK: Main clock frequency
φ: Machine clock (CPU operating clock) frequency
1/φ: Machine cycle (CPU operating clock period)
See "5.1 Clocks", for details.
Note:
When the reset is occurred in the stop mode or sub-clock mode, the oscillation stabilization wait time of
15
2 /HCLK (approx. 8.19 ms, using at HCLK = 4 MHz oscillation) is required.
See "5.6 Oscillation Stabilization Wait Interval" for details.
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