Configuration Of Address Match Detection Function - Fujitsu F2MCTM-16LX Hardware Manual

CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
22.3

Configuration of Address Match Detection Function

This section lists and details the registers used by the address match detection function.
List of Registers and Reset Values of Address Match Detection Function
Figure 22.3-1 List of Registers and Reset Values of Address Match Detection Function
Address detection control register 0(PACSR0)
Address detection control register 1(PACSR1)
Detection address setting register 0(PADR0): Low
Detection address setting register 0(PADR0): Middle
Detection address setting register 0(PADR0): High
Detection address setting register 1(PADR1): Low
Detection address setting register 1(PADR1): Middle
Detection address setting register 1(PADR1): High
Detection address setting register 2(PADR2): Low
Detection address setting register 2(PADR2): Middle
Detection address setting register 2(PADR2): High
Detection address setting register 3(PADR3): Low
Detection address setting register 3(PADR3): Middle
Detection address setting register 3(PADR3): High
Detection address setting register 4(PADR4): Low
Detection address setting register 4(PADR4): Middle
Detection address setting register 4(PADR4): High
Detection address setting register 5(PADR5): Low
Detection address setting register 5(PADR5): Middle
Detection address setting register 5(PADR5): High
×: Undefined
508
bit
7 6 5 4
0 0 0 0
bit 15 14 13 12
0 0 0 0
bit 7 6 5 4
bit 15 14 13 12
bit 7 6 5 4
bit 15 14 13 12
bit 7 6 5 4
bit 15 14 13 12
bit 7 6 5 4
bit 15 14 13 12
bit 7 6 5 4
bit 7 6 5 4
bit 15 14 13 12
bit 7 6 5 4
bit 15 14 13 12
bit 7 6 5 4
bit 15 14 13 12
bit 7 6 5 4
bit 15 14 13 12
bit 7 6 5 4
3 2 1 0
0 0 0 0
11 10 9 8
0 0 0 0
3 2 1 0
11 10 9 8
3 2 1 0
11 10 9 8
3 2 1 0
11 10 9 8
3 2 1 0
11 10 9 8
3 2 1 0
3 2 1 0
11 10 9 8
3 2 1 0
11 10 9 8
3 2 1 0
11 10 9 8
3 2 1 0
11 10 9 8
3 2 1 0