Serial Status Register (Ssr) - Fujitsu F2MCTM-16LX Hardware Manual

20.4.3

Serial Status Register (SSR)

This register checks the transmission and reception status and error status, and
enables and disables the transmission and reception interrupts.
Serial Status Register (SSR)
Figure 20.4-4 Configuration of the Serial Status Register (SSR)
Address
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
SSR0:000023
H
PE ORE FRE RDRF TDRE BDS RIE TIE
SSR1:00002B
H
R
R/W : Read/Write
R : Read only
: Initial value
R R R R R/W R/W R/W
bit7 bit0
Initial value
00001000
B
bit8
TIE Transmission interrupt request enable bit
0 Disables transmission interrupt
1 Enables transmission interrupt
bit9
RIE Reception interrupt request enable bit
0 Disables reception interrupt
1 Enables reception interrupt
bit10
BDS Transfer direction selection bit
0 LSB first (transfer from lowest bit)
1 MSB first (transfer from highest bit)
bit11
TDRE Transmission data empty flag bit
0 Transmission data register is full.
1 Transmission data register is empty.
bit12
RDRF Reception data full flag bit
0 Reception data register is empty
1 Reception data register is full
bit13
FRE Framing error flag bit
0 No framing error occurred
1 A framing error occurred
bit14
ORE Overrun error flag bit
0 No overrun error occurred
1 An overrun error occurred
bit15
PE Parity error flag bit
0 No parity error occurred
1 A parity error occurred
CHAPTER 20 LIN-UART
397