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CHAPTER 16 8-/16-BIT PPG TIMER
16.2.2
Block Diagram of 8-/16-bit PPG Timer D
The 8-/16-bit PPG timer D consists of the following blocks.
Block Diagram of 8-/16-bit PPG Timer D
PPGD reload
register
Operation
mode control
signal
PPGD temporary
buffer (PRLBHD)
Count start value
PPGD underflow
(to PPGC)
PPGC underflow
(from PPGC)
-
: Undefined (from PPG0)
Reservation: Reserved bit
HCLK : Oscillation clock frequency
φ
: Machine clock frequency
*
: The interrupt output of 8-/16- bit PPG timer D is combined to one interrupt by OR circuit with the interrupt
request output of PPG timer C.
288
Figure 16.2-3 Block Diagram of 8-/16-bit PPG Timer D
PRLLD
PRLHD
(Low level side)
(High level side)
Reload register
L/H selector
Reload
Under-
flow
PPGD down counter
(PCNTD)
CLK
Timebase timer output
(512/HCLK)
φ
Resource clock (1/
)
φ
Resource clock (2/
)
φ
Resource clock (4/
)
φ
Resource clock (8/
)
φ
Resource clock (16/
)
Count
clock
selector
High level side data bus
Low level side data bus
PPGD operation mode control register (PPGCD)
PEN1
-
PE1 PIE1 PUF1 MD1 MD0
2
Select signal
Clear
PPGD
output latch
Invert
PPG output control circuit
MD0
3
Select signal
PCS2
PCS1
PCS0 PCM2 PCM1 PCM0
PPGC/D count clock select register (PPGCD)
Re-
served
R
Interrupt
request
S
Q
output*
Pin
PPGD
PPGC
output
-
REV
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