9.1
9.1.1
Mode Pins .................................................................................................................................. 163
9.1.2
Mode Data ................................................................................................................................. 164
9.1.3
CHAPTER 10 I/O PORTS ................................................................................................ 167
10.1
I/O Ports .......................................................................................................................................... 168
10.2
I/O Port Registers ........................................................................................................................... 169
10.2.1
Port Data Register (PDR) .......................................................................................................... 170
10.2.2
10.2.3
10.2.4
10.2.5
Input Level Select Register ........................................................................................................ 176
11.1
Overview of Timebase Timer .......................................................................................................... 180
11.2
11.3
11.3.1
11.4
Interrupt of Timebase Timer ........................................................................................................... 187
11.5
11.6
11.7
12.1
Overview of Watchdog Timer ......................................................................................................... 196
12.2
12.3
Watchdog Timer Registers ............................................................................................................. 201
12.3.1
12.4
12.5
12.6
13.1
Overview of 16-bit I/O Timer ........................................................................................................... 210
13.2
13.2.1
13.2.2
13.3
13.3.1
13.3.2
13.3.3
Timer Data Register (TCDT) ..................................................................................................... 220
13.3.4
13.3.5
13.3.6
13.4
vii