Input Capture Register (Ipcp) - Fujitsu F2MCTM-16LX Hardware Manual

13.3.5

Input Capture Register (IPCP)

Input capture register stores the counter value fetched from 16-bit free-run timer by the
capture operation.
The IPCP register is the 16-bit read-only register and has the input capture registers 0 to
3 (IPCP0 to IPCP3).
Input Capture Register (IPCP)
IPCP0 (upper): 007921
IPCP0 (lower): 007920
IPCP1 (upper): 007923
IPCP1 (lower): 007922
IPCP2 (upper): 007925
IPCP2 (lower): 007924
IPCP3 (upper): 007927
IPCP3 (lower): 007926
R : Read only
X : Undefined
When the trigger edge of the capture operation (ICSnm: set by EGn1, EGn0 or EGm1, EGm0) is detected
by the IN0 to IN3 pins, the counter value of the 16-bit free-run timer is stored in the input capture registers
0 to 3 corresponding to each pin.
However, the input capture registers 0 and 1 can be selected a signal from the LIN-UART as the input
signal (ICE: selected by IEI bit). See "13.3.6 Input Capture Edge Register (ICE)" for details.
The input capture register can be read, but can not be written.
n =0,2 m = n+1
Note:
Always use a word instruction (MOVW) to read the input capture register.
Figure 13.3-5 Input Capture Register (IPCP)
Address
bit15 bit14 bit13 bit12 bit11 bit10 bit9
H
CP15 CP14
R R
bit7 bit6
H
CP07 CP06
R
bit15 bit14 bit13 bit12 bit11 bit10 bit9
H
CP15 CP14
R R
bit7 bit6
H
CP07 CP06
R
bit15 bit14 bit13 bit12 bit11 bit10 bit9
H
CP15 CP14
R R
bit7 bit6
H
CP07 CP06
R
bit15 bit14 bit13 bit12 bit11 bit10 bit9
H CP15 CP14
R R
bit7 bit6
H
CP07 CP06
R
CHAPTER 13 16-Bit I/O TIMER
CP13 CP12 CP11 CP10 CP09 CP08
R R R R R
bit5 bit4 bit3 bit2 bit1
CP05 CP04 CP03 CP02 CP01
R R R R R R
CP13 CP12 CP11 CP10 CP09 CP08
R R R R R
bit5 bit4 bit3 bit2 bit1
CP05 CP04 CP03 CP02 CP01
R R R R R R
CP13 CP12 CP11 CP10 CP09 CP08
R R R R R
bit5 bit4 bit3 bit2 bit1
CP05 CP04 CP03 CP02 CP01
R R R R R R
CP13 CP12 CP11 CP10 CP09 CP08
R R R R R
bit5 bit4 bit3 bit2 bit1
CP05 CP04 CP03 CP02 CP01
R R R R R R
Reset value
bit8
XXXXXXXX
B
R
bit0
CP00
XXXXXXXX
B
R
bit8
XXXXXXXX
B
R
bit0
CP00
XXXXXXXX
B
R
bit8
XXXXXXXX
B
R
bit0
CP00
XXXXXXXX
B
R
bit8
XXXXXXXX
B
R
bit0
CP00
XXXXXXXX
B
R
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