Timebase Timer Control Register (Tbtc) - Fujitsu F2MCTM-16LX Hardware Manual

11.3.1

Timebase timer control register (TBTC)

The timebase timer control register (TBTC) provides the following settings:
• Selecting the interval time of the timebase timer
• Clearing the counter value of the timebase timer
• Enabling or disabling the interrupt request when an overflow occurs
• Checking and clearing the state of the interrupt request flag when an overflow occurs
Timebase Timer Control Register (TBTC)
15 14
Address
Re-
0000A9
H
served
R/W
R/W
W
X
Figure 11.3-2 Timebase Timer Control Register (TBTC)
8
13 12 11 10 9
TBIE TBOF TBR TBC1 TBC0
R/W R/W W R/W R/W
: Read/write
: Write only
: Indeterminate
: Reset value
: Undefined
Reset value
1 X X 0 0 1 0 0
B
bit9 bit8
TBC1 TBC0 Interval time select bit
0 0
12
2 /HCLK (approx. 1.0 ms)
0 1 14
2 /HCLK (approx. 4.1 ms)
1 0 16
2 /HCLK (approx. 16.4 ms)
1 1 19
2 /HCLK (approx. 131.1 ms)
HCLK: Oscillation clock
The parenthesized values are provided when the oscillation clock
operates at 4 MHz.
bit10
TBR Timebase timer counter clear bit
Read
0
"1" is always read.
1
bit11
TBOF Overflow interrupt request flag bit
Read
0 Without overflow of selected
count bit
1 With overflow of selected
count bit
bit12
TBIE Overflow interrupt enable bit
0 Disabling of overflow interrupt request
1 Enabling of overflow interrupt request
bit15
Re-
served
1 "1" is always set.
CHAPTER 11 TIMEBASE TIMER
Write
Clear timebase timer counter.
Clear TBOF bit.
No effect
Write
Being clear.
No effect
Reserved bit
185