Reception Complete Register (Rcr) - Fujitsu F2MCTM-16LX Hardware Manual

21.4.17

Reception Complete Register (RCR)

At completion of storing received message in the message buffer (x), RCx becomes 1.
If RIEx of the reception complete interrupt enable register (RIER) is 1, an interrupt
occurs.
Register Configuration
Figure 21.4-17 Configuration of the Reception Complete Register (RCR)
Address
CAN1: 000089
Address
CAN1: 000088
R/W : Read/Write
Register Function
Conditions for RCx = 0
Write 0 to RCx.
After completion of handling received message, write 0 to RCx to set it to 0. Writing 1 to RCx is ignored.
1 is read when a Read Modify Write instruction is performed.
Note:
If setting to 1 by completion of the receive operation and clearing to 0 by writing occur at the same
time, the bit is set to 1.
bit15 bit14 bit13
RC15 RC14 RC13
H
R/W R/W R/W
bit7 bit6 bit5
RC7 RC6 RC5
H
R/W R/W R/W
bit12 bit11 bit10
RC12 RC11 RC10
R/W R/W R/W
bit4 bit3 bit2
RC4 RC3 RC2
R/W R/W R/W
bit9 bit8 RCR1(Upper)
RC9 RC8 Reset value
0 0 0 0 0 0 0 0
R/W R/W
bit1 bit0 RCR1(Lower)
RC1 RC0 Reset value
0 0 0 0 0 0 0 0
R/W R/W
B
B
473