Interrupt Of Timebase Timer - Fujitsu F2MCTM-16LX Hardware Manual

11.4

Interrupt of Timebase Timer

The timebase timer generates an interrupt request (interval timer function) when the
interval time bit in the timebase timer counter corresponding to the interval time set by
the timebase timer control register carries (overflows).
Interrupt of Timebase Timer
• The timebase timer continues incrementing for as long as the main clock (with a half frequency of the
oscillation clock) is inputted.
• When the interval time set by the interval time select bits in the timebase timer control register (TBTC:
TBC1, TBC0) is reached, the interval time select bit corresponding to the interval time selected in the
timebase timer counter carries and an overflow generates.
• When the interval time select bit overflows, the overflow interrupt request flag bit in the timebase timer
control register (TBTC: TBOF) is set to "1".
• When the overflow interrupt request flag bit in the timebase timer control register is set (TBTC: TBOF
= 1) with an interrupt enabled (TBTC: TBIE = 1), an interrupt request is generated.
• When the selected interval time is reached, the overflow interrupt request flag bit in the timebase timer
control register (TBTC: TBOF) is set regardless of whether an interrupt is enabled or disabled (TBTC:
TBIE)
• To clear the overflow interrupt request flag bit (TBTC: TBOF), disable a timebase timer interrupt at
interrupt processing (TBTC: TBIE = 0) or mask a timebase timer interrupt by using the ILM bit in the
processor status (PS) to write "0" to the TBOF bit.
Note:
An interrupt request is issued immediately if you enable interrupts (TBTC: TBIE = 1) with the overflow
interrupt request flag bit in the timebase timer control register set (TBTC: TBOF = 1).
Correspondence between Timebase Timer Interrupt and EI
• The timebase timer does not correspond to EI
• For details of the interrupt number, interrupt control register, and interrupt vector address, see "3.2
Interrupt Vector".
CHAPTER 11 TIMEBASE TIMER
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