Configuration Of Watchdog Timer; Block Diagram Of Watchdog Timer - Fujitsu F2MCTM-16LX Hardware Manual

12.2

Configuration of Watchdog Timer

The watchdog timer consists of the following blocks:
• Count clock selector
• Watchdog timer counter (2-bit counter)
• Watchdog reset generator
• Counter clear control circuit
• Watchdog timer control register (WDTC)

Block Diagram of Watchdog Timer

Watchdog timer
Generation of reset
Shift to sleep mode
Shift to timebase
timer mode
Shift to watch mode
Shift to stop mode
Main clock
(2 division of HCLK)
Sub clock
SCLK*
HCLK : Oscillation clock
SCLK : Sub clock
* : SCLK is 2 division or 4 division of the clock inputted to the low-speed oscillation pin (X0A and X1A) or
internal CR oscillation clock. The division ratio is set by the SCDS bit of the PLL/subclock control
register (PSCCR). (See "CHAPTER 5 CLOCKS".)
Figure 12.2-1 Block Diagram of Watchdog Timer
Watchdog timer control register (WDTC)
PONR WRST ERST
2
Count clock
Counter
selector
clear control
circuit
4
(Timebase timer counter)
⋅ ⋅ ⋅
× × × ×
1 2 8
2 2 2
(Watch counter)
⋅ ⋅ ⋅
× × × ×
1 2 5
2 2 2
SRST WTE WT1 WT0
Start up
2-bit
counter
Clear
× × × × ×
9 10 11 12 13
2 2 2 2 2
× × × × ×
6 7 8 9 10
2 2 2 2 2
CHAPTER 12 WATCHDOG TIMER
Watch timer control register (WTC)
WDCS
To internal
Watchdog reset
reset
generation
generation
circuit
circuit
4
× × × ×
14 16 17 18
2 2 15 2 2 2
× × × ×
11 12 13 14 15
2 2 2 2 2
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