Timer Control Status Registers (High) (Tmcsr:h) - Fujitsu F2MCTM-16LX Hardware Manual

14.3.1

Timer Control Status Registers (High) (TMCSR:H)

The timer control status registers (High) (TMCSR:H) set the operation mode and count
clock.
This section also explains the bit 7 in the timer control status registers (Low)
(TMCSR:L).
Timer Control Status Registers (High) (TMCSR:H)
Figure 14.3-3 Timer Control Status Registers (High) (TMCSR:H)
Address:
15
TMCSR2 : 000065
H
TMCSR3 : 000067
H
R/W : Read/Write
X ; Indeterminate
−
: Undefined
: Reset value
14 13 12 11 10 9
CSL1 CSL0 MOD2
− − − −
R/W R/W R/W
bit9
MOD2
0
0
0
0
1
1
bit9
MOD2
X
X
X
X
bit11
CSL1
0
0
1
1
T: Machine cycle
8 7
Reset value
MOD1 MOD0
XXXX0000
B
R/W R/W
bit8 bit7
Operating mode select bit (internal clock mode)
(CSL1, 0="00
MOD1 MOD0
Input pin function
0 0 Trigger disable
0 1
1 0 Trigger input
1 1
X 0
Gate input
X 1
bit8 bit7
Operating mode select bit (event count mode)
MOD1 MOD0
Input pin function
0 0
0 1
1 0 Trigger input
1 1
bit10
Count clock select bit
CSL0
Count clock
0
1 Internal clock mode
0
1 Event count mode
CHAPTER 14 16-BIT RELOAD TIMER
", "01 ", "10 ")
B B B
Valid edge, level
−
Rising edge
Falling edge
Both edges
"L" level
"H" level
(CSL1, 0="11 ")
B
Valid edge
− −
Rising edge
Falling edge
Both edges
Count clock cycle
1
2 T
3
2 T
5
2 T
External event clock
245