Ppgc Operation Mode Control Register (Ppgcc) - Fujitsu F2MCTM-16LX Hardware Manual

CHAPTER 16 8-/16-BIT PPG TIMER
16.3.1

PPGC Operation Mode Control Register (PPGCC)

The PPGC operation mode control register (PPGC0) provides the following settings for
the operation of 8-/16-bit PPG timer C:
• Enabling or disabling operation of 8-/16-bit PPG timer C
• Switching between pin functions (enabling or disabling pulse output)
• Enabling or disabling underflow interrupt
• Setting underflow interrupt request flag
This section explains the PPGCC function only. The PPGCE has the same function as
the PPGCC, and the 8-/16-bit PPPG timer C and E is set.
PPGC Operation Mode Control Register (PPGCC)
Figure 16.3-2 PPGC Operation Mode Control Register (PPGCC)
Address:
chC PPGCC 000048
Other channel:
chE PPGCE 00004C
R/W : Read/Write
W : Write only
X : Indeterminate
−
: Undefined
: Reset value
292
7 6
5 4 3
H
PEN0 PE0 PIE0 PUF0
−
R/W R/W R/W R/W
H
2 1 0 Reset value
Re-
0 X 0 0 0 X X 1
served
bit 0
− −
R/W
Re-
served
1 Always set to "1"
bit 3
PUF0
0
No underflow
1
Underflow
bit 4
PIE0 Underflow interrupt enable bit
0 Interrupt request disable
1 Interrupt request enable
bit 5
PE0
General-purpose I/O port
0
(pulse output disable)
1
PPGC output (pulse output enable)
bit 7
PEN0
Couting disable
0
(holds "L" level output)
1 Counting enable
B
Reserved bit
Underflow generation flag bit
Read Write
Clears PUF0 bit
No effect
PPG0 pin output enable bit
PPG0 operation enable bit