Fujitsu F2MCTM-16LX Hardware Manual page 116

CHAPTER 5 CLOCKS
Table 5.3-1 Functions of Clock Selection Register (CKSCR) (2/2)
Bit name
bit10 MCS:
PLL clock select bit
bit9 CS1, CS0:
bit8 Multiplication rate
select bits
100
This bit indicates the main clock or PLL clock to be selected as the machine clock.
When the machine clock is switched from the main clock to the PLL clock (CKSCR: MCS =
1 → 0), the clock mode changes from main clock mode to PLL clock mode after the PLL
clock oscillation stabilization wait time is generated.The timebase timer is cleared
automatically.The oscillation stabilization wait time taken when the clock mode is switched
from main clock to PLL clock is fixed at 2
oscillation clock frequency of 4 MHz).The oscillation stabilization wait time taken when the
machine clock is switched from subclock mode to PLL clock mode follows the values
specified in the oscillation stabilization wait time select bits (CKSCR: WS1, WS0).
Any reset causes the bit to return to the reset value.
Notes:
1) When both of the MCS and SCS bits contain 0, the SCS bit supersedes the MCS bit,
thereby setting the subclock mode.
2) When switching from the main clock to PLL clock (CKSCR: MCS = 1 → 0), use the
timebase timer interrupt enable bit (TBTC: TBIE) or interrupt level mask register (ILM:
ILM2 to 0) to disable timebase timer interrupts before writing 0 to the PLL clock select
bit.
These bits select the PLL clock multiplication rate with the CS2 bit in the PLL/subclock
control register (PSCCR).
One of five types of PLL clock multiplication rate can be selected.
Any reset causes the bit to return to the reset value.
Setting of CS0, CS1, and CS2
CS2 CS1
0
0
0
0
1
1
Note: Setting CS2 to CS0 bits to "111
When PSCCR: CS2 is set to "1", do not set CKSCR: CS1 and CS0 to "11
When the PLL clock is selected (CKSCR: MCS = 0), writing is inhibited. To change
the multiplier, write 1 to the PLL clock select bit (CKSCR: MCS), update the
multiplication rate select bits (CKSCR: CS1, CS0), then set the PLL clock select bit
(CKSCR: MCS) back to 0.
Function
14
/HCLK (about 4.1 ms during operation at an
CS0 PLL clock multiplication rate
0 0
0 1
1 0
1 1
1 0
1 1
" is prohibited.
B
× 1
× 2
× 3
× 4
× 6
Setting disabled
".
B