Fujitsu F2MCTM-16LX Hardware Manual page 471

Control status register (CSR-upper)
Table 21.4-2 Function of Each Bit of the Control Status Register (CSR:H)
Bit Name
bit15 TS:
Transmit status
bit
bit14 RS:
Receive status bit
bit13 Undefined bits
to
bit11
bit10 NT:
Node status
transition flag
bit9 NS1, NS0:
bit8 Node status bits
This bit indicates whether a message is being transmitted.
At read:
0: Message not being transmitted
1: Message being transmitted
This bit is set 0 even while error and overload frames are transmitted.
This bit indicates whether a message is being received.
At read:
0: Message not being received
1: Message being received
• While a message is on the bus, this bit becomes 1. Therefore, this bit is also 1 while a
message is being transmitted. This bit does not necessarily indicates whether a receiving
message passes through the acceptance filter.
• As a result, when this bit is 0, it implies that the bus operation is stopped (HALT = 1);
the bus is in the intermission/bus idle or a error/overload frame is on the bus.
When reading: The value is undefined.
When writing: No effect
When the node status changes from increment transition or off bus into error active, this bit is
set to "1". The condition that this bit is set to "1" is as follows. At this time, the interruption
is generated for the node status interruption permission bit (NIE) = "1".
") → Warning ("01
1) Error active ("00
B
") → Error passive ("10
2) Warning ("01
B
") → Bus off ("11
3) Error passive ("10
B
") → Error active ("00
4) Bus off ("11
B
Note:
In parentheses, the value of NS1 and the NS0 bit is indicated.
At Write:
"0": Cleared
"1": Not possible to set (No effect)
At read by the instruction of the read-modify-write type:
Always read "1".
These bits indicate the current node status.
For detail information, see "21.4.3 Correspondence between Node Status Bit and Node
Status".
Function
")
B
")
B
")
B
")
B
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